1. Field of the Invention
The present invention relates to a method of fabricating an integrated circuit (IC), and more particularly to a method of fabricating a semiconductor device.
2. Description of Related Art
MOS transistors are basic structures widely used in various semiconductor devices such as memory devices, image sensors, or displays. A typical MOS transistor includes a silicon oxide dielectric layer, a gate conductive layer, and a heavily-doped source/drain contact regions. Along with the decrease of a line width, the size of the semiconductor device is reduced. A channel length of the typical MOS transistor is reduced as a gate width is reduced. Since a threshold voltage becomes smaller and a subthreshold current is increased, a short channel effect is induced. On the other hand, after the gate length is reduced, an electric field between a source and a drain is enhanced, which causes a hot carrier effect. Thus, a lot of carriers may be generated in the channel at a position near the drain region, thus resulting in an electrical breakdown effect. In order to prevent the breakdown phenomenon, it is necessary to maintain a proper channel length. As such, the formed MOS transistor is not applicable.
In order to solve the above problem, a lightly doped drain (LDD) structure is adopted. In the LDD structure, concentration of the source/drain region near the channel is reduced, i.e., an LDD region is formed, so as to alleviate the hot carrier effect resulting from the enhancement of the electric field between the source and the drain. However, since the dopant concentration of the LDD region is low, the resistance is relatively high, which results in a reduced device current and a slow operating speed of the device, and the power consumption is increased.
It is a method for improving the operating speed of the transistor that a mechanical-stress in the channel is controlled to change the mobility of electrons and holes in the channel. The conventional art has proposed a material, for example, SiGe epitaxy used as a major component of the source/drain contact region of the p-channel MOS (PMOS) transistor. Compared with material characteristics of silicon, the SiGe, when used as the major component of the source/drain contact region, exerts a compressive stress on the channel due to a larger atomic volume of Ge. Therefore, the SiGe when used as a major material of the source/drain contact region can enhance the mobility of holes, thus further improving the performance of the device.
For a PMOS transistor, the Boron implanted in the doped region is liable to diffuse outwards to channel, thus resulting in a short channel effect. In order to solve the problem of Boron diffusion, a method of adding an undoped SiGe buffer layer between the doped region and the substrate has been proposed. However, in non-doped SiGe, Boron may also easily diffuse to the channel region, so usually the undoped SiGe layer must be thick enough to achieve a sufficient barrier effect. However, the resistance of the undoped SiGe is high, so the thicker the undoped SiGe buffer layer is, the greater the effect on the resistance of the doped region is, and the weaker the performance of the device will be. On the other hand, a current leakage problem resulting from the substrate and the buffer layer interface deficiencies is in urgent need of being solved.